FIG. 1 shows a typical configuration for an integrated circuit including a flash EEPROM memory array 100 and circuitry enabling programming, erasing, reading, and overerase correction for memory cells in the array 100. The flash EEPROM array 100 is composed of individual cells, such as cell 102. Each cell has a drain connected to a bitline, such as bit line 104, each bitline being connected to a bitline switch circuit 106 and column decoder 108. Sources of the array cells are connected to each other and VSL, which is the common source signal, while their gates are each connected by a wordline to a row decoder 110.
The row decoder 110 receives voltage signals from a power supply 112 and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor or state machine 114. Likewise, the bitline switch circuit 106 receives voltage signals from the power supply 112 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 114. Voltages provided by the power supply 112 are provided as controlled by signals received from processor 114.
The column decoder 108 provides signals from particular bitlines to sense amplifiers or comparators 116 as controlled by a column address signal received from processor 114. The power supply 112 supplies voltages to column decoder 108 and bit lines 104. The sense amplifiers 116 further receive a signal from reference cells of reference array 118. With signals from the column decoder 108 and reference array 118, the sense amplifiers 116 then each provide a signal indicating a state of a bitline relative to a reference cell line to which it is connected through data latches or buffers 120 to processor 114.
To program a cell in the flash memory array 100, high gate-to-source voltage pulses are provided to the cell from power supply 112 while a source of the cell is grounded. For instance, during programming multiple gate voltage pulses typically of 10 V are each applied for approximately three to six microseconds to a cell, while a drain voltage of the cell is set to 4.5 V and its source is grounded. The large gate-to-source voltage pulses enable electrons flowing from the source to drain to overcome an energy barrier to produce “hot electrons,” some of which are accelerated across a thin dielectric layer enabling the electrons to be driven onto a floating gate of the cell. This programming procedure, termed “hot electron injection” results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
To erase a cell in the flash memory array 100, a procedure known as Fowler-Nordheim tunneling is utilized wherein relatively high negative gate-to-source voltage pulses are applied for a few tenths of a second each. For instance, during erase multiple gate voltage pulses of −10 V are applied to a cell, while a source of the cell is set to 5.5 V and its drain is floating. The large negative gate-to-source voltage pulses enable electrons to tunnel from the floating gate of a cell reducing its threshold.
After erasure, there is a concern with “overerase.” Overerased cells have a threshold voltage that is too low and provide leakage current even when the gate-to-source voltage is at 0V. The cell leakage will form a non-negligible bit line current, which leads to reading and programming errors. Therefore, overerase correction is performed to reduce this bit line current. During overerase correction, all of the cells on a bit line in the flash memory array 100 have the same gate-to-source voltage with the source grounded. The drain voltage of the cell is set to around 5V. Again, hot electrons will be injected into the floating gate to raise the threshold voltages of the cells.
During programming, the bit line current of a bit line is composed of a cell current with the cell biased at programming condition and any cell currents provided by the unselected cells from the bit line. In general, the unselected cells have the gate-to-source voltage at ground level. During overerase correction, the bit line current is composed of all of the cell currents coming from all of the cells connected to the bit line. If overerase correction is done by bit line, all of the cells have equal gate-to-source voltages. If the overerase correction is done by a cell, the selected cell will have a different gate-to-source voltage from the other cells.
To represent a data bit, the floating gate of a cell is programmed or erased as described above. In a programmed state, the threshold voltage of a cell is typically set at greater than 5.0 volts, while the threshold voltage of a cell in an erased state is typically limited below 3.0 volts. To read a cell, a control gate voltage between 3.0 and 6.5 volts, typically 5 V, is applied. The 5 V read pulse is applied to the gate of an array cell as well as a cell in reference array 118 having a threshold near 3.5 V. In a programmed state with an array cell in array 100 having a threshold above 5.0 V, current provided by the reference cell with a threshold of 3.5 V will be greater indicating a programmed cell exists. In an erased state with a threshold of a cell in array 100 below 3.0 V, current provided by the array cell will be greater than the reference cell with a threshold of 3.5 V indicating an erased cell. To verify programming or erase, a read voltage is similarly applied to both a cell in the array and to cells in the reference array 118. For programming, a reference cell having a threshold of 5.0 V is used for a comparison, while for erase, a reference cell having a threshold of 3.0 V is used for comparison.
FIG. 2 is a circuit diagram of a portion of a flash memory, specifically illustrating two bit lines 104 each including two cells 102 and associated circuitry for generating bit line voltages VBL (shown as VBLo through VBLn) at the respective drains of cells 102 during programming and overerase correction. The common source line is shown grounded. Although only two bit lines 104 and two word lines are illustrated, it should be understood that any number of bit lines and words lines, and thus any number of cells, may be included in a memory array. Respective word line signals WLo through WLn are coupled to the control gates of cells 102. There are multiple bit lines selected by the column decoder (FIG. 1), which activate bit switches 124 associated with each bit line. Once a corresponding bit switch 124 is turned on, the corresponding bit line 104 is activated and the cell 102 is activated via the word line signal.
The memory array also typically includes multiple I/Os, such as eight I/Os in byte mode and 16 I/Os in word mode. Each I/O includes multiple bit lines 104 and one bit line is selected from each I/O for reading or programming, i.e., one bit line each is selected from 8 I/Os in byte mode (for a total of 8 bit lines and eight bits) and one bit line each is selected from 16 I/Os in word mode (for a total of 16 bit lines and 16 bits) for reading or programming. Each I/O corresponds to one internal data line signal, DL (shown as DL[0] through DL[n]), and multiple bitlines. Signal DL[n] is a global signal shared by many local bit lines with a common I/O, and DL[0] is a global signal shared by many local bit lines with a common I/O, although FIG. 2 illustrates only one bit line 104 per I/O. If a “0” is to be programmed to a selected cell 102 from a selected bit line 104 from a selected I/O, the respective PMOS QPL associated with the I/O is turned on. If “1” is to be programmed to the cell, the corresponding PMOS QPL from the I/O is turned off.
Power supply 112 (also shown in FIG. 1) may include a charge pump circuit or external power supply to supply the bit line current on a bit line needed during programming or overerase correction. The supply voltage VDQ1 is regulated to a target drain voltage value VDQ2 by, for example, differential amplifier 122. Bit switches 124, illustrated as pass gate transistors QBS0, QBS1, QBS2, are turned on by being biased to a high voltage level VPP by the addressed column decoder 108 and transfer the voltage of VDQ2 to the local bit line 104. In the illustrated example, each bit switch 124 includes three MOS pass transistors, but the number of pass transistors can vary from chip design to chip design.
The target value for voltage VDQ2 is set to ((Ra+Rb)/Ra)*VR. VR is a reference voltage provided by, for example, a reference voltage sub-circuit (not shown). A capacitor 126 is coupled between node VDQ2 and ground. This capacitor reduces the variation in VDQ2 when its source, VDQ1, is pumped. A leakage path circuit discharges VDQ2 once VDQ2 is over the target value, particularly during the time when VDQ2 is initially generated by the charge pump circuit, to prevent overshoot. A capacitor 130 is also connected between the gate of PMOS QP0 and node VDQ2. Capacitor 130 responses VDQ2 to QP0 in real time. The bit switches 124 are shown biased with a high voltage level VPP to allow the passing of VDQ2 to local bit lines during programming or overerase connection. The transistor size of the bit switch 124 is typically limited to save size.
During operation, there is a voltage drop across the bit switch 124 and PMOS QPL of each bit line when current flows therethrough. The magnitude of the voltage drop depends on the magnitude of the current through each cell 102, i.e., the larger the bit line current, the larger the voltage drop. This voltage drop decreases the local bit line voltage VBL (shown as VBLo through VBLn in FIG. 2) to below the target level VDQ2. The programming capability is significantly reduced during the initial programming stage because of the increased current in cells 102. Overerase correction is also degraded. As a cell is gradually programmed, the cell gains electrical charge and the cell current decreases gradually. The local VBL raises to approach VDQ2 as the local bit line current decreases.
The voltage drop of VBL also has an impact on overerase correction. The efficiency of overerase correction is reduced significantly and may result in failure, i.e., the cell cannot be overerase corrected successfully in the limited time duration set by design.
The circuit programming technique illustrated in FIG. 2 and described above does not provide a fixed VBL during programming of each cell 102. If VDQ2 is designed high to compensate for the voltage drop across bit switches 124, there are reliability concerns when the bit line current is reduced through programming or overerase correction. The reliability concerns include stressing out the interface state and degrading the endurance cycle of the cell. If VBL is raised too close to VDQ2, VBL can cause a soft program on non-selected cells on the selected bit line. Generated hot holes impact the Si—SiO2 interface and generate interface states. The interface states impact cell threshold voltage and change the erasing characteristics of the cell as well as programming.
Therefore, there remains a need for a circuit and methodology for providing a bit line voltage to a memory cell or cells that is insensitive to the cell current.